Location
London

Hours
Full Time

Salary
Negotiable

About the Role
At Apple, we work daily to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our Advanced Technology group, you will have the rare and rewarding opportunity to craft upcoming products, which will delight and encourage millions of Apple’s customers every single day. Do your life’s best work here at Apple! This role is for a Design Verification Engineer who will enable bug-free first silicon for the mixed-signal designs in our new London team. Responsibilities include all phases of pre-silicon verification, such as construction of verification environments, coding of test scenarios and assertions, and close collaboration with Analog and Digital Design engineers. You will define and design self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The role spans from concept discussions, verification strategy definition, to execution of verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and includes performance-based analysis, power-related analysis and scenario design for early power estimation, delivery of tests for design and test engineering teams, gate-level verification (power and timing), and lab bring-up support. A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team’s DNA.

Experience
- Knowledge of SystemVerilog test-bench language and UVM (Universal Verification Methodology)
- Hands-on experience with constrained random verification environments
- Basic design background to support verification results analysis
- Experience in AI/ML is desired
- Hands-on experience with Assertion Based Verification
- Familiarity with system design using C++, Python or Verilog
- Familiarity with FPGA emulation platforms

About you
Proactive, innovative and collaborative engineer with a passion for solving complex verification challenges. Strong communication skills and ability to work closely with cross-functional teams. Proficiency in English is required.

Qualifications
Master’s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent.